OVERVIEW

The CHI Network Interconnect (CHI NIC) is a scalable, high-performance interconnect IP designed to connect processors, memory subsystems, and peripherals in modern SoCs. Based on a configurable crossbar architecture, it provides low-latency, high-bandwidth communication using a packet-based transport mechanism.

The interconnect supports AMBA CHI compliant interfaces, enabling communication between request nodes (RN), home nodes (HN), and slave nodes (SN) using Request, Response, and Data channels. The architecture focuses on efficient transaction transport and routing without implementing cache coherency, making it suitable for non coherent or loosely coupled system designs.

To achieve high throughput, the interconnect supports parallel processing across independent CHI channels and multiple outstanding transactions. Configurable arbitration, QoS, and ordering controls allow designers to optimize latency, fairness, and bandwidth utilization based on system requirements. The interconnect also supports NoC cascading, enabling scalable expansion to large multi-node systems.

The design provides flexibility for system integration through configurable address mapping and internal data width, allowing trade offs between performance, power, and area.

Robust system management features include advanced interrupt handling, per-channel watchdog timers for detecting stalled transactions, and independent software-controlled reset for each interface to enable localized fault isolation.

To support complex clocking environments, each interface can operate in an independent clock domain. Register slicing enables clean clock domain crossings and improved timing closure, while internal clock gating reduces dynamic power consumption.

Delivered as a synthesizable RTL IP optimized for power, performance, and area (PPA), the CHI NIC integrates into AMBA-based SoC designs requiring scalable, high-bandwidth, non-coherent interconnect solutions.