OVERVIEW
enable seamless interoperability between CHI (Coherent Hub Interface) and AXI (Advanced eXtensible Interface) domains. It serves as a critical integration component in SoCs where coherent interconnects must interface with AXI-based peripherals, memory subsystems, or legacy IP.
The bridge translates CHI request, response, and data messages into AXI channel-based transactions while preserving transaction semantics, data integrity, and system-level ordering requirements. It efficiently converts CHI multi-beat transfers into AXI burst operations and performs flexible data width adaptation through upsizing, downsizing, and beat packing/unpacking mechanisms.
To ensure reliable operation, the design includes transaction ID mapping, outstanding transaction tracking, and ordering enforcement aligned with AXI protocol rules. It also incorporates buffering and flow control logic to bridge CHI's credit-based scheme with AXI's valid/ready handshake, enabling high-throughput and low-latency data movement.
The CHI2AXI bridge can be configured to handle coherency boundaries by terminating or converting CHI coherent transactions into non-coherent AXI accesses, depending on system requirements. Additionally, it supports clock domain crossing (CDC) and reset domain management, allowing flexible deployment across different clock and reset environments.
Overall, the CHI2AXI bridge provides a scalable, configurable, and efficient solution for integrating CHI-based coherent fabrics with AXI-based subsystems, making it well-suited for modern high-performance SoC designs.
KEY HIGHLIGHTS
Converts CHI request, response, and data messages into AXI channel-based transactions (Req/Dat → AR, AW, W and Rsp/Dat → R, B)
Ø Translates CHI multibeat data transfers into AXI burst operations Ø Maps CHI transfer size and byte-enable fields into AXI beat count, data width, and strobe
Ø Maps CHI transaction ID / source ID to AXI ID field
Ø Tracks CHI transaction IDs and enforces AXI ordering rules on responses
Ø Supports data width conversion with efficient upsizing/downsizing and bit packing/unpacking
Ø Converts CHI error responses into standard AXI response codes (SLVERR, DECERR)
Ø Buffers requests and responses and adapts CHI credit-based flow control to AXI valid/ready handshaking
Ø Maintains outstanding transaction tracking to manage multiple in-flight operations across CHI and AXI
Ø Handles coherency by terminating or converting CHI coherent transactions into non-coherent AXI accesses based on system configuration
Ø Supports optional clock domain crossing (CDC) using asynchronous FIFOs between CHI and AXI domains
Ø Provides reset domain synchronization or isolation between CHI and AXI interfaces
